1. Field of the Invention
The present invention relates to semiconductor devices, and, more particularly, to non-volatile memory devices and methods of forming the same.
2. Description of Related Art
NAND type non-volatile memory devices may be used in portable electronic products for a variety of functions. For example, NAND type non-volatile memory devices may be used to store image data in digital cameras and/or to store micro codes in portable telephones. NAND type non-volatile memory devices may include storage cell gate patterns and select gate patterns serially connected to at least one bit line pattern in an active region of a semiconductor substrate. The devices may be capable of performing data read and write operations to implement functions suitable for portable electronic products. The cell gate patterns may be located between the select gate patterns. The select gate patterns and the cell gate patterns may respectively correspond to select transistors and cell transistors.
However, the electrical properties of NAND type non-volatile memory devices may be degraded as the devices are scaled-down. This may be due to several factors. For example, NAND type non-volatile memory devices may include select gate patterns and storage cell gate patterns on the same active region, each of which may be driven by different voltages. When cell gate patterns for a specific bit line are programmed, the electrical properties of cell gate patterns for other bit lines adjacent to the specific bit line may be degraded. In particular, the cell and select gate patterns may see increased electric field intensity as distances therebetween are reduced. The increased electric field intensity may be accompanied by increased electrical coupling between the cell and select gate patterns. As such, hot electrons may be more easily injected into the gate insulating layer. As data read and write operations are repeatedly performed, the hot electrons injected into the gate insulating layer may speed up and/or slow down the data read and write operations, which may cause the NAND type non-volatile memory devices to malfunction. Thus, the electrical properties of the NAND type non-volatile memory devices may be rapidly degraded as the number of read and write operations increases.
Also, U.S. Pat. No. 5,807,778 to Lee discloses a method of manufacturing a shallow trench source EPROM cell. As noted in the Abstract of the Lee patent, the inventive cell comprises a source area which is at a lower plane than the drain region, and a program charge is transferred to the floating gate through the source-side injector. Instead of using a self-aligned high-energy n-type dopant implant at the source side to form the source side injector as used with previous cells, which can be difficult to control, etching the substrate before impurity doping allows for the controllable formation of a sharp point of doped silicon, and allows for improved programming at a lower voltage.